1. Field of the Invention
This invention relates to computer systems and more particularly to system power management functions in computer systems.
2. Description of the Related Art
Power management is becoming an increasingly significant consideration in computers systems. For example, some personal computers (PCs) are being designed to be powered on all of the time. Thus, the PC is beginning to adopt modes of operation that are similar in some respects to a video cassette recorder (VCR) which is always powered on but is often in a xe2x80x9csleepxe2x80x9d state. Reducing power consumption in order to reduce operating costs and environmental impact of PCs is also a factor being considered. Thus, PCs are adopting increasingly complex power management functions. In addition to placing a PC in a low power or sleep states, power management function must also wake-up the PC from sleep states in response to certain conditions caused by signal levels on external pins or internal timers.
In addition to power management functions becoming more complex, levels of integration have increased as more and more functions have been integrated onto core logic chipsets. For example, such functions as the real time clock, keyboard controller, IDE interface and interface to the universal serial bus (USB) have been integrated onto core logic chipsets. That increasing level of integration causes pin counts to increase, which places pressure on package costs. There exists a need to provide the necessary power management functions in the context of controlling the increasing pin counts.
Accordingly, the invention provides core logic functions partitioned across two chips interconnected by a serial bus. The serial bus, which is placed in a power savings mode, is used to communicate the existence of a wake-up event from one chip of the partition to another. Accordingly, the invention provides according to one embodiment, an apparatus for system power management. The apparatus includes a first integrated circuit having a first bus interface circuit for interfacing to a bus. The first bus interface circuit is responsive to a reduced power consumption state to maintain each of the signal lines on the bus driven by the first integrated circuit at a fixed voltage level. A second integrated circuit includes a second bus interface circuit for interfacing to the bus. The second bus interface circuit includes a circuit responsive to the reduced power consumption state to maintain each signal line on the bus driven by the second integrated circuit at a fixed voltage. The second interface is responsive to a wake-up event to change a signal line on the bus driven by the second integrated circuit from a first to a second voltage level, thereby providing a wake-up indication to the first integrated circuit indicating that a wake-up event has occurred.
In another embodiment, a method provides an indication to a first integrated circuit that a wake-up event has occurred on an input terminal of a second integrated circuit where the first and second integrated circuit are coupled by a bus. The bus is initially in a reduced power consumption state. One of the signal lines of the bus is changed from a first voltage level to a second voltage level in response to a wake-up event recognized by the second integrated circuit. The bus is changed from the reduced power consumption state to a normal power consumption state in response to the at least one signal line being at the second voltage level.